1. Field of the Invention
This invention relates to a method and apparatus for reducing power usage of embedded memory in a semiconductor device. More particularly, it relates to the reduction or elimination of power drain by unaccessed or inactive embedded SRAM memory blocks or other clocked or synchronized embedded memory components.
2. Background of Related Art
In general, it is important to reduce power usage of integrated circuits where possible, particularly in the case of sophisticated power-hungry integrated circuits which include embedded memory, e.g., static random access memory (SRAM). Generally, integrated circuits operate less efficiently as their temperature increases. A reduction in power usage provides less heat dissipation by the underlying integrated circuit. Increased heat dissipation requires increased heat sinking, fan capacity or other structure to cool the integrated circuit, enlarging the size and reducing the speed and performance of the product.
FIG. 5 shows pertinent portions of a conventional integrated circuit including embedded synchronized memory, e.g., a DSP 320 such as the DSP1620 commercially available from LUCENT TECHNOLOGIES. A DSP core 300 is embedded in the DSP 320, as are other DSP logic 302 and SRAM memory array 310. The SRAM memory array 310 comprises a plurality of individual SRAM memory blocks 312. The DSP core 300 communicates with the SRAM memory blocks 312 through address bus 304, data bus (or busses if the SRAM memory blocks 312 are dual port SRAM) 306, and control lines 308.
Conventional communication lines between DSP core 300 and SRAM memory blocks 312 are shown in more detail in FIG. 6. A clock line 360 and a read/write line 362 communicate in common with all SRAM memory blocks 312a-312d. Individually decoded enable lines 350, 352, 354, 356 separately enable each of the individual SRAM memory blocks 312a-312d.
FIG. 7 shows the clock signal from the DSP core 300 input directly into SRAM memory block 312a through a buffer formed by a serial connection of two inverters 360, 362.
In the example of a digital signal processor (DSP), embedded SRAM typically operates faster than external SRAM because it allows a DSP to operate without wait states which might otherwise be required when accessing external SRAM. However, on-chip embedded, synchronized SRAM comes at the price of increased power usage by the DSP.
One conventional solution to the increased power usage by embedded SRAMs is to remove the common clock signal simultaneously from all SRAM memory blocks when the SRAM memory array is not being accessed. However, this solution causes all SRAM memory to be placed in an inactive state. To subsequently access any individual SRAM memory block in the SRAM array, the clock must be reapplied to the entire SRAM array, thus activating all embedded SRAM memory blocks.
Thus, conventional embedded SRAM array structures require common clocking which activates all SRAM memory blocks together, causing significant power usage, increased heat dissipation and shorter battery life. As a result, a design balance must conventionally be made as between the amount of on-chip embedded SRAM and an overall minimization of power usage by the DSP.